(1) Field of the Invention
The present invention relates to semiconductor devices including metal interconnections of, for example, copper and methods for fabricating the semiconductor devices.
(2) Background Art
With recent increase in integration degree of semiconductor integrated circuits, interconnect patterns come to have higher densities, and thus parasitic capacitance between interconnects has increased. The increase in parasitic capacitance causes an interconnect delay of signals. Therefore, reduction of the parasitic capacitance between interconnects is an important issue in semiconductor integrated circuits that need to operate at high speed. To reduce the parasitic capacitance between interconnects, reductions of a relative dielectric constant between interconnects and a relative dielectric constant of an interlayer insulating film are currently studied.
A silicon dioxide (SiO2) film (relative dielectric constant: 3.9 to 4.2) has been conventionally used as a material for an insulating film provided between interconnects in many cases. In some semiconductor integrated circuits, the relative dielectric constant of an insulating film is reduced by using a fluorine (F)-containing SiO2 film (relative dielectric constant: 3.5 to 3.8). In addition, a semiconductor device in which a low-dielectric-constant film (hereinafter, referred to as a low-κ film) of a carbon-containing silicon oxide film (i.e., a SiOC film) having a relative dielectric constant of three or less is used as an insulating film between interconnects in order to reduce parasitic capacitance between interconnects is currently proposed.
However, when a low-κ film made of SiOC is used as an insulating film between interconnects, low film strength of the low-κ film causes a problem in which the SiOC film suffers from physical damage in a chemical mechanical polishing (CMP) process for forming an interconnect. To avoid this, a method of forming, for example, a protective film (i.e., a CMP damage preventing film) which is not susceptible to damage, on a low-strength film such as a SiOC film is proposed (see, for example, Japanese Laid-Open Patent Publication Nos. 2004-146798 and 2005-051214). In general, a low-κ film is susceptible to damage and, thereby, increases its dielectric constant during dry etching and ashing. The use of the CMP damage preventing film described above is also effective to prevent this increase.
Now, a conventional semiconductor device will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view illustrating an example of a semiconductor device using a SiOC film as an insulating film between interconnects.
As illustrated in FIG. 7, the conventional semiconductor device includes: a first insulating film 1 formed on a substrate (not shown), having a first interconnect trench 8 at its upper portion and made of, for example, a SiO2 film; a first metal interconnect 2 formed on the inner face of the first interconnect trench 8 and constituted by a barrier metal 2a of, for example, tantalum nitride (TaN) and a conductive film 2b formed on the barrier metal 2a to fill the first interconnect trench 8 and made of, for example, copper (Cu); a second insulating film 3 formed on the first insulating film 1 and the first metal interconnect 2 and made of, for example, silicon carbide (SiC); a third insulating film 4 formed on the second insulating film 3 and made of a low-κ film such as a SiOC film; and a fourth insulating film 5 formed on the third insulating film 4 and made of, for example, SiO2. A via hole 7 is formed in the second insulating film 3 and a lower portion of the third insulating film 4. A second interconnect trench 10 is formed in the fourth insulating film 5 and an upper portion of the third insulating film 4 and is connected to the via hole 7. The conventional semiconductor device further includes: a metal via 9 constituted by a barrier metal 6a made of, for example, TaN and formed on the inner face of the via hole 7 and a conductive film 6b made of, for example, Cu; and a second metal interconnect 6 constituted by the barrier metal 6a formed on the inner face of the second interconnect trench 10 and the conductive film 6b and connected to the first metal interconnect 2 via the metal via 9.
Now, a conventional method for fabricating a semiconductor device with the foregoing structure will be described with reference to FIGS. 8A through 8D. FIGS. 8A through 8D are cross-sectional views showing the conventional method for fabricating a semiconductor device.
First, as shown in FIG. 8A, a first insulating film 1 made of, for example, SiO2 is formed on a substrate (not shown), and then an interconnect trench pattern is formed on the first insulating film 1 by photolithography. Thereafter, the first insulating film 1 is selectively etched by dry etching, thereby forming a first interconnect trench 8. Subsequently, a barrier metal 2a made of, for example, TaN is formed on the inner face of the first interconnect trench 8, and then a conductive film 2b made of, for example, Cu is deposited on the barrier metal 2a to fill the first interconnect trench 8. Then, redundant Cu is removed by chemical mechanical polishing (CMP), thereby forming a first metal interconnect 2 constituted by the barrier metal 2a and the conductive film 2b. 
Next, as shown in FIG. 8B, a second insulating film 3 made of, for example, SiC is deposited over the first insulating film 1 and the first metal interconnect 2 to a thickness of 50 nm. Subsequently, a third insulating film 4 of a low-κ film such as a SiOC film is deposited over the second insulating film 3 to a thickness of 500 nm, and then a fourth insulating film 5 made of, for example, SiO2 is deposited by plasma CVD over the third insulating film 4 to a thickness of 50 nm.
Thereafter, as shown in FIG. 8C, a hole pattern is formed on the fourth insulating film 5 by photolithography, and then the second insulating film 3, the third insulating film 4 and the fourth insulating film 5 are selectively etched by dry etching, thereby forming a via hole 7 in which the upper face of the first metal interconnect 2 is exposed.
Thereafter, as shown in FIG. 8D, a mask is formed on the third insulating film 4, and then an upper portion of the third insulating film 4 and a portion of the fourth insulating film 5 surrounding the via hole 7 are selectively removed by dry etching, thereby forming a second interconnect trench 10 having a given shape. Subsequently, a barrier metal 6a made of, for example, TaN is formed on the inner faces of the second interconnect trench 10 and the via hole 7, and then a conductive film 6b made of, for example, Cu is deposited on the barrier metal 6a to fill the via hole 7 and the second interconnect trench 10. Then, redundant Cu is removed by CMP, thereby forming a metal via 9 and a second metal interconnect 6 constituted by the barrier metal 6a and the conductive film 6b at a time.
In the conventional method for fabricating a semiconductor device, the fourth insulating film 5 is provided as a CMP damage preventing film. Thus, it is possible to prevent the third insulating film 4 from being damaged during CMP in the process step shown in FIG. 8D.